Datasheet

Chapter 14. UART Modules 14-29
Operation
14.5.2.2.1 AC ‘97 Low-Power Mode
A general-purpose I/O (GPIO) must be used as an AC ‘97 reset output pin. UART1
monitors the first three time slots of each Tx frame to detect the power-down condition for
the AC ‘97 digital interface. The power-down condition is detected as follows:
1. The first 3 bits of slot 1 must be set, indicating that the Tx frame and slots 1 and 2
are valid.
2. Slot 2 holds the address of the power-down register (0x26) in the external AC ‘97
device.
3. Slot 3 contains a 1 in the fourth bit (bit 12/PR4 in power-down register 1), as defined
in the AC ’97 specification.
Low-power mode can be left through either a warm or cold reset. The CPU performs a
warm reset by setting MODCTL[AWR] for at least 1 µs. This negates R
TS, which is used
as the frame sync output in AC ‘97 mode. The CPU performs a cold reset in two steps:
1. Writes a 0 to whichever GPIO is being used as the active low AC ‘97 reset pin for
the minimum time specified in the AC ‘97 specification.
2. Writes a 0 to UART1’s MODCTL[ACRB] (bit 7). The CPU sets this bit after writing
a 1 to the GPIO used for the AC ‘97 reset pin.
Step 2 is required so UART1 knows when an AC ‘97 cold reset is occurring.
14.5.2.3 Receiver
The receiver is enabled through its UCRn, as described in Section 14.3.10, “UART
Command Registers (UCRn).” Figure 14-34 shows receiver functional timing.