Datasheet

14-38 MCF5407 User’s Manual
Operation
• Interrupt handling—Consists of SIRQ (sheet 4), which is executed after the UART
module generates an interrupt caused by a change-in-break (beginning of a break).
SIRQ then clears the interrupt source, waits for the next change-in-break interrupt
(end of break), clears the interrupt source again, then returns from exception
processing to the system monitor.
14.5.6.1 UART Module Initialization Sequence
NOTE:
UART module registers can be accessed by word or byte
operations, but only data byte D[7:0] is valid.
Table 14-19 shows the UART module initialization sequence.
Table 14-19. UART Module Initialization Sequence
Register Setting
UCRn Reset the receiver and transmitter—UART or modem modes.
Reset the mode pointer (MISC[2–0] = 0b001)—UART or modem modes.
UIVRn Program the vector number for a UART module interrupt—UART or modem modes.
UIMRn Enable the preferred interrupt sources—UART or modem modes.
UACRn Initialize the input enable control (IEC bit)—UART mode only.
UCSRn Select the receiver and transmitter clock. Use timer as source if required—UART mode only.
UMR1n If preferred, program operation of receiver ready-to-send (RxRTS bit)—UART mode only.
Select receiver-ready or FIFO-full notification (RxRDY/FFULL bit)—UART or modem modes.
Select character or block error mode (ERR bit)—UART mode only.
Select parity mode and type (PM and PT bits)—UART mode only.
Select number of bits per character (B/Cx bits)—UART mode only.
UMR2n Select the mode of operation (CMx bits)—UART or modem modes.
If preferred, program operation of transmitter ready-to-send (TxRTS)—UART mode only.
If preferred, program operation of clear-to-send (TxCTS bit)—UART mode only.
Select stop-bit length (SBx bits)—UART mode only.
RXLVL UART1 only, UART or modem modes—Choose Rx FIFO full threshold level.
TXLVL UART1 only, UART or modem modes—Choose Tx FIFO empty threshold level.
MODCTL Modem mode only
Choose the desired modem mode.
Choose whether msb or lsb is to be transferred first.
Choose 0- or 1-bit delay between rising edge of frame sync and first bit of time slot 1.
Choose 1 or 2 DMA channels to service UART1.
Activate/deactivate AC ‘97 warm and cold resets.
UCRn Enable the receiver and transmitter—UART or modem modes.