Datasheet

Chapter 15. Parallel Port (General-Purpose I/O) 15-3
Parallel Port Operation
• PADAT settings do not affect inputs. PADAT bit values determine the corresponding
logic levels of pins configured as outputs.
• PADAT can be written to anytime. A read from PADAT returns values of
corresponding pins configured as general-purpose I/O in the PAR and designated as
inputs by the PADDR.
Table 15-3 shows relationships between PADAT bits and parallel port pins when PADAT is
accessed. The effect differs when the parallel port pin is an input or output.
The following results occur when a parallel port pin is configured as an input:
• When the PADAT is read, the value returned is the logic value on the pin.
• When the PADAT is written, the register contents are updated without affecting the
logic value on the pin.
The following results occur when a parallel port pin is configured as an output:
• When the PADAT is read, the register contents are returned and the pin is the logic
value of the register.
• When the PADAT is written, the register contents are updated and the pin is the logic
value of the register.
These relationships are also described in Table 15-3.
NOTE:
Although external devices cannot access the MCF5407’s
on-chip memories or MBAR, they can access any parallel port
module registers in the SIM.
15 0
Field PADAT
Reset 0000_0000_0000_0000
R/W R/W
Address Address MBAR+0x248
Figure 15-3. Port A Data Register (PADAT)
Table 15-3. Relationship between PADAT Register and Parallel Port Pin (PP)
PP Status PADAT R/W Effect on PADAT Effect on PP
Input
Read Register bit value is the pin’s logic value No effect. Source of logic value
Write Register contents updated No effect on the logic value at the pin
Output
Read Register contents are returned Pin is the logic value of the register bit
Write Register contents updated Pin is the logic value of the register bit