Datasheet

17-6 MCF5407 User’s Manual
Overview
A[31:0] Address Bus I/O 17-7
BCLKO Bus clock out Clock/reset O 17-13
BD
Bus driven Bus arbitration O 17-13
BE
[3:0]/BWE[3:0] Byte enable[3:0]/Byte write enable[3:0] Chip select O 17-16
BG
Bus grant Bus arbitration I 17-12
BR
Bus request Bus arbitration O 17-12
CAS
[3:0] Column address strobe DRAM O 17-16
CLKIN Clock input Clock/reset I 17-13
CS[
7:0] Chip selects[7:0] UART O 17-15
CTS
[1:0] Clear-to-send Serial module I 17-19
DACK[1:0] DMA acknowledge DMA O 17-18
DIVIDE[2:0] Divide control PCLK to CLKIN Clock/reset I 17-15
DRAMW
DRAM write DRAM O 17-16
DREQ
[1:0] DMA request DMA I 17-17
D[31:0] Data Bus I/O 17-8
EDGESEL Sync edge select DRAM I 17-17
HIZ
High impedance Debug I 17-20
IRQ7
, IRQ5,
IRQ3
, IRQ1
Interrupt request Interrupt control I 17-12
MTMOD[3:0] Motorola test mode Debug I 17-20
OE Output enable Chip select O 17-16
PP[15:0] Parallel port Parallel port I/O 17-19
PSTCLK Processor clock out Debug O 17-20
PSTDDATA[7:0] Processor status/debug data Debug O 17-20
PS_CONFIG[1:0] Port size configuration Clock/reset I 17-14
R/W
Read/Write Bus I/O 17-8
RAS
[1:0] Row address strobe DRAM O 17-16
RSTI
Reset In Clock/reset I 17-13
RST
O Reset Out Clock/reset O 17-13
R
TS[1:0] Request-to-send Serial module O 17-19
RxD[1:0] Receive data Serial module I 17-19
SCAS
Synchronous column address strobe DRAM O 17-17
SCKE Synchronous clock enable DRAM O 17-17
SCL Serial clock line I
2
C I/O 17-20
SDA Serial data line I
2
C I/O 17-20
SIZ[1:0] Size Bus I/O 17-8
Table 17-2. MCF5407 Alphabetical Signal Index (Continued)
Abbreviation Signal Name Function I/O Page