Datasheet

Chapter 17. Signal Descriptions 17-7
MCF5407 Bus Signals
17.2 MCF5407 Bus Signals
The bus signals provide the external bus interface to the MCF5407.
17.2.1 Address Bus
The address bus provides the address of the byte or most-significant byte (MSB) of the
word or longword being transferred. The address lines also serve as the DRAM addressing,
providing multiplexed row and column address signals. When an external device has
ownership of the MCF5407 bus, the device must drive the address bus and assert TS
or AS
to indicate the start of a bus cycle. During an interrupt acknowledge access, A[4:2] indicate
the interrupt level being acknowledged.
17.2.1.1 Address Bus (A[23:0])
The lower 24 bits of the address bus become valid when TS is asserted. A[4:2] indicate the
interrupt level during interrupt acknowledge cycles.
17.2.1.2 Address Bus (A[31:24]/PP[15:8])
These multiplexed pins can serve as the most-significant byte of the address bus, or as the
most-significant byte of the parallel port. Programming the PAR in the system integration
module (SIM) determines the function of each of these eight multiplexed pins. These pins
are programmable on a bit-by-bit basis.
SRAS Synchronous row address strobe DRAM O 17-17
T
A Transfer acknowledge Bus I/O 17-9
TCK Test clock JTAG I 17-22
TDI/DSI Test data input/Development serial input JTAG I 17-22
TDO/DSO Test data output/Development serial output JTAG O 17-22
TIN[1:0] Timer input Timer I 17-19
TIP
Transfer in progress Bus O 17-10
TMS/BKPT
Test mode select/Breakpoint JTAG I 17-21
TM[2:0] Transfer modifier Bus O 17-10
TOUT[1:0] Timer outputs Timer O 17-19
TRST
/DSCLK Test reset/Development serial clock JTAG I 17-21
TS
Transfer start Bus I/O 17-9
TT[1:0] Transfer type Bus O 17-10
TxD[1:0] Transmit data Serial module O 17-18
Table 17-2. MCF5407 Alphabetical Signal Index (Continued)
Abbreviation Signal Name Function I/O Page