Datasheet

17-12 MCF5407 User’s Manual
Interrupt Control Signals
17.3 Interrupt Control Signals
The interrupt control signals supply the external interrupt level to the MCF5407 device.
17.3.1 Interrupt Request (IRQ1/IRQ2, IRQ3/IRQ6, IRQ5/IRQ4,
and IRQ7)
The IRQ1, IRQ3, IRQ5, and IRQ7 signals are the default interrupt request signals (IRQn).
However, by setting the appropriate bit in the interrupt port assignment register (IRQPAR),
IRQ1
, IRQ3, and IRQ5 can be changed to function as IRQ2, IRQ6, and IRQ4, respectively.
See Section 9.2.4, “Interrupt Port Assignment Register (IRQPAR).”
17.4 Bus Arbitration Signals
The bus arbitration signals provide the external bus arbitration control for the MCF5407.
17.4.1 Bus Request (BR)
The BR output indicates to an external arbiter that the processor is requesting to be bus
master for one or more bus cycles. BR
is negated when the MCF5407 begins an access to
the external bus with no other internal accesses pending. BR
remains negated until another
internal request occurs.
17.4.2 Bus Grant (BG)
An external arbiter asserts the BG input to indicate that the MCF5407 can take control of
the bus on the next rising edge of CLKIN. When the arbiter negates BG
, the MCF5407 will
release the bus as soon as the current transfer completes. The external arbiter must not grant
the bus to any other master until both BD
and BG are negated.
Table 17-10. TM[2:0] Encodings for TT = 11 (Interrupt Level)
TM[2:0] Transfer Modifier
000 CPU Space
001 Interrupt level 1 acknowledge
010 Interrupt level 2 acknowledge
011 Interrupt level 3 acknowledge
100 Interrupt level 4 acknowledge
101 Interrupt level 5 acknowledge
110 Interrupt level 6 acknowledge
111 Interrupt level 7 acknowledge