Datasheet

17-14 MCF5407 User’s Manual
Clock and Reset Signals
17.5.5 Data/Confi guration Pins (D[7:0])
This section describes data pins, D[7:0], that are read at reset for configuration. Table 17-11
shows pin assignments.
17.5.5.1 D[7:5,3]—Boot Chip-Select (CS0) Configuration
D[7:5,3] determine defaults for the global chip select (CS0), the only chip select valid at
reset. These signals correspond to bits in chip-select configuration register 0 (CSCR0).
17.5.5.2 D7—Auto Acknowledge Configuration (AA_CONFIG)
At reset, the enabling and disabling of auto acknowledge for boot CS0 is determined by the
logic level driven on D7 at the rising edge of RSTI
. AA_CONFIG is multiplexed with D7
and sampled only at reset. The D7 logic level is reflected as the reset value of CSCR[AA].
Table 17-12 shows how the D7 logic level corresponds to the auto acknowledge timing for
CS0
at reset. Note that auto acknowledge can be disabled by driving a logic 0 on D7 at reset.
17.5.5.3 D[6:5]—Port Size Configuration (PS_CONFIG[1:0])
The default port size value of the boot CS0 is determined by the logic levels driven on
D[6:5] at the rising edge of RSTI
, which are reflected as the reset value of CSCR[PS]. Table
17-13 shows how the logic levels of D[6:5] correspond to the CS0
port size at reset.
Table 17-11. Data Pin Configuration
Pin Function
D7 Auto-acknowledge configuration (AA_CONFIG)
D[6:5] Port size configuration (PS_CONFIG[1:0])
D4 Address configuration (ADDR_CONFIG/D4)
D3 Byte enable configuration (BE_CONFIG)
D[2:0] Divide control (DIVIDE[2:0])
Table 17-12. D7 Selection of CS0 Automatic Acknowledge
D7 (CSCR0[AA]) Boot CS0 AA
0 Disabled
1 Enabled with 15 wait states
Table 17-13. D6 and D5 Selection of CS0 Port Size
D[6:5] (CSCR0[PS]) Boot CS0 Port Size
00 32-bit port
01 8-bit port
1x 16-bit port