Datasheet

Chapter 17. Signal Descriptions 17-17
DMA Controller Module Signals
17.7.4 Synchronous DRAM Column Address Strobe (SCAS)
The synchronous DRAM column address strobe (SCAS) is registered during synchronous
mode to route directly to the SCAS
signal of SDRAMs.
17.7.5 Synchronous DRAM Row Address Strobe (SRAS)
The synchronous DRAM row address strobe output (SRAS) is registered during
synchronous mode to route directly to the SRAS
signal of external SDRAMs.
17.7.6 Synchronous DRAM Clock Enable (SCKE)
The synchronous DRAM clock enable output (SCKE) is registered during synchronous
mode to route directly to the SCKE signal of external SDRAMs. This signal provides the
clock enable to the SDRAM.
17.7.7 Synchronous Edge Select (EDGESEL)
The synchronous edge select input (EDGESEL) helps select additional output hold times
for signals that interface to external SDRAMs. It provides the following three modes of
operation for SDRAM control signals:
• When EDGESEL is tied high, SDRAM control signals change on the rising edge of
CLKIN.
• When EDGESEL is tied low, SDRAM control signals change on the falling edge of
CLKIN.
• When EDGESEL is tied to the external clock (normally buffered CLKIN), which
drives the SDRAM and other devices, SDRAM signals are generated within the
MCF5407 make a transition on the rising edge of the SDRAM clock. See
Figure 11-14 on page 11-19. This loop-back configuration provides additional
output hold time for MCF5407 interface signals provided to the SDRAM. In this
case, the SDRAM clock operates at the CLKIN frequency, with a possible slight
phase delay.
17.8 DMA Controller Module Signals
The DMA controller module uses the signals in the following subsections to provide
external request for either a source or destination.
17.8.1 DMA Request (DREQ[1:0]/PP[6:5])
The DMA request pins (DREQ[1:0]/PP[6:5]) can serve as the DMA request inputs or as
two bits of the parallel port, as determined by individually programmable bits in the PAR.
These inputs are asserted by a peripheral device to request an operand transfer between that
peripheral and memory by either channel 0 or 1 of the on-chip DMA.