Datasheet

17-18 MCF5407 User’s Manual
Serial Module Signals
17.8.2 Transfer Modifier/DMA Acknowledge
(TM[2:0]/DACK[1:0])
Although the MCF5407 provides similar encodings on TM[2:0], DMA acknowledgement
pins (DACK[1:0]) are now combined with PP[3:2]/TM[1:0], resulting in three-to-one
multiplexed signals, PP[3:2]/TM[1:0]/DACK[1:0]. TM2 is still multiplexed only with PP4.
When properly connected, TM[2:0] can be used in MCF5407 designs as on MCF5307
designs, or DACK[1:0] can be used for DMA transfers, as shown in Figure 17-2.
To enable DACK[1:0], first enable TM[1:0] through the PAR and then program the
interrupt assignment register (IRQPAR) in the MCF5407 SIM module to enable bits 0–1.
When IRQPAR[ENBDACK1] = 1 and PAR is programmed to enable TM1, DACK1 for
DMA channel 1 is driven in place of TM1 for DMA transfers. Clearing ENBDACK1
disables this function and only the TM1 encoding is driven. Likewise, setting ENBDACK0
enables DACK0 to be driven; clearing ENBDACK0 disables this function and drives the
TM0 encoding.
Although the MCF5407 TM[2:0] signals can drive DMA access encoding, the bit positions
of these encodings differ from the MCF5307. Single-address access indication is now
encoded on TM2 when the PAR is set to enable the transfer modifier signal and an external
master or DMA transfer is occurring. This encoding is driven by TM0 on the MCF5307. In
addition, DMA acknowledge encodings are driven on TM[1:0] on the MCF5407, as
opposed to TM[2:1] on the MCF5307.
17.9 Serial Module Signals
The signals in the following sections are used to transfer serial data between the two UART
modules and external peripherals.
17.9.1 Transmitter Serial Data Output (TxD)
In UART mode, TxD is held high (mark condition) when the transmitter is disabled, idle,
or operating in the local loop-back mode. Data is shifted out least-significant bit (lsb) first
on TxD on the falling edge of the clock source. For UART1 in modem mode, TxD is held
low when the transmitter is disabled or idle. Data is shifted out on TxD on the rising edge
of the clock signal driving UART1’s CTS
input. UART1 transfers can be specified as either
lsb or msb first.
MCF5307 Function Pin Pin MCF5407 Function
Single/dual cycle access TM0 TM0 DMA 0 acknowledge
DMA 0 acknowledge configuration TM1 TM1 DMA 1 acknowledge
DMA 1 acknowledge configuration TM2 TM2 Single/dual cycle access
Figure 17-2. MCF5307 to MCF5407 TM[2:0] Pin Remapping