Datasheet

Chapter 18. Bus Operation 18-1
Chapter 18
Bus Operation
This chapter describes data-transfer operations, error conditions, bus arbitration, and reset
operations. It describes transfers initiated by the MCF5407 and by an external bus master,
and includes detailed timing diagrams showing the interaction of signals in supported bus
operations. Chapter 11, “Synchronous/Asynchronous DRAM Controller Module,”
describes DRAM cycles.
18.1 Features
The following list summarizes bus operation features:
• Up to 32 bits of address and data
• 8-, 16-, and 32-bit port sizes
• Byte, word, longword, and line size transfers
• Bus arbitration for external devices
• Burst and burst-inhibited transfer support
• Internal termination for core and DMA bus cycles
• External termination of bus cycles controlled by an external bus master
Note that, throughout this manual, an overbar indicates an active-low signal.
18.2 Bus and Control Signals
Table 18-1 summarizes MCF5407 bus signals described in Chapter 17, “Signal
Descriptions.”
Table 18-1. ColdFire Bus Signal Summary
Signal Name Description MCF5407 Master External Master Edge
AS
Address strobe O I Falling
A[31:0] Address bus O I Rising
BE
/BWE
1
Byte enable/Byte write enable O O Falling
CS
[7:0]
1
Chip selects O O Falling
D[31:0] Data bus I/O I/O Rising