Datasheet

18-2 MCF5407 User’s Manual
Bus Characteristics
18.3 Bus Characteristics
The MCF5407 uses an input clock signal (CLKIN) to generate its internal clock and
outputs BCLKO, which is provided for backwards compatibility for MCF5307 designs.
CLKIN is the bus clock rate, where all bus operations are synchronous to the rising edge of
CLKIN. Some of the bus control signals (BE
/BWE, OE, CSx, and AS) are synchronous to
the falling edge, shown in Figure 18-1. Bus characteristics may differ somewhat for
interfacing with external DRAM.
Figure 18-1. Signal Relationship to CLKIN for Non-DRAM Access
18.4 Data Transfer Operation
Data transfers between the MCF5407 and other devices involve the following signals:
IRQ[7,5,3,1] Interrupt request I I Rising
OE
1
Output enable O I Falling
R/W
Read/write O I Rising
SIZ[1:0] Transfer size O I Rising
T
A Transfer acknowledge I O Rising
TIP
Transfer in progress O Three-state Rising
TM[2:0] Transfer modifier O Three-state Rising
TS
Transfer start O I Rising
TT[1:0] Transfer type O Three-state Rising
1
These signals change after the falling edge. In Chapter 20, “Electrical Specifications,” these signals are specified
off the rising edge because CLKIN is squared up internally.
Table 18-1. ColdFire Bus Signal Summary (Continued)
Signal Name Description MCF5407 Master External Master Edge
Rising-Edge
Signals
Falling-Edge
Signals
Inputs
t
vo
t
ho
t
vo
t
ho
t
si
t
hi
CLKIN
t
vo
=Propagation delay of signal relative to CLKIN edge
t
ho
=Output hold time relative to CLKIN edge
t
si
=Required input setup time relative to CLKIN edge
t
hi
=Required input hold time relative to CLKIN edge