Datasheet

Chapter 18. Bus Operation 18-3
Data Transfer Operation
• Address bus (A[31:0])
• Data bus (D[31:0])
• Control signals (TS
and TA)
•AS
, CSx, OE, BE/BWE
• Attribute signals (R/W, SIZ, TT, TM, and TIP)
The address bus, write data, TS
, and all attribute signals change on the rising edge of
CLKIN. Read data is latched into the MCF5407 on the rising edge of CLKIN. AS
, CSx,
OE
, and BE/BWE change on the falling edge.
The MCF5407 bus supports byte, word, and longword operand transfers and allows
accesses to 8-, 16-, and 32-bit data ports. Transfer parameters such as port size, the number
of wait states for the external slave being accessed, and whether internal transfer
termination is enabled, can be programmed in the chip-select control registers (CSCRs) and
DRAM control registers (DACRs).
For aligned transfers larger than the port size, SIZ[1:0] behaves as follows:
• If bursting is used, SIZ[1:0] stays at the size of transfer.
• If bursting is inhibited, SIZ[1:0] first shows the size of the transfer and then shows
the port size.
Table 18-2 shows encoding for SIZ[1:0].
Figure 18-2 shows the byte lanes that external memory should be connected to and the
sequential transfers if a longword is transferred for three port sizes. For example, an 8-bit
memory should be connected to D[31:24] (BE0
). A longword transfer takes four transfers
on D[31:24], starting with the MSB and going to the LSB.
Table 18-2. Bus Cycle Size Encoding
SIZ[1:0] Port Size
00 Longword
01 Byte
10 Word
11 Line