Datasheet

Chapter 18. Bus Operation 18-9
Data Transfer Operation
Figure 18-7. Write Cycle Flowchart
The write cycle timing diagram is shown in Figure 18-8.
Figure 18-8. Basic Write Bus Cycle
Table 18-4 describes the six states of a basic write cycle.
18.4.5 Fast-Termination Cycles
Two clock-cycle transfers are supported on the MCF5407 bus. In most cases, this is
impractical to use in a system because the termination must take place in the same half
clock during which AS
is asserted. Because this is atypical, it is not referred to as the
zero-wait-state case but is called the fast-termination case. A fast-termination cycle is one
in which an external device or memory asserts T
A as soon as TS is detected. This means
that the MCF5407 samples T
A on the rising edge of the second cycle of the bus transfer.
Figure 18-9 shows a read cycle with fast termination. Note that fast termination cannot be
used with internal termination.
1. Sample TA low
1. Tree-state D[31:0]
2. Start next cycle
System
1. Set R/W
to write
2. Place address on A[31:0]
3. Assert TT[1:0], TM[2:0], TIP
,
and SIZ[1:0]
4. Assert TS
5. Assert AS
6. Place data on D[31:0]
7. Negate TS
1. Decode address
2. Store data on D[31:0]
3. Assert TA
1. Negate TA
MCF5407
A[31:0], TT[1:0]
R/W
TIP
TS
D[31:0]
T
A
S0 S1 S2 S3 S4 S5
Write
CLKIN
AS
, CSx
BWEx
TM[2:0], SIZ[1:0]