Datasheet

18-12 MCF5407 User’s Manual
Data Transfer Operation
18.4.7.1 Line Transfers
A line is a 16-byte-aligned, 16-byte value. Despite the alignment, a line access may not
begin on the aligned address; therefore, the bus interface supports line transfers on multiple
address boundaries. Table 18-5 shows allowable patterns for line accesses.
18.4.7.2 Line Read Bus Cycles
Figure 18-12 shows line read with zero wait states. The access starts like a basic read bus
cycle with the first data transfer sampled on the rising edge of S4, but the next pipelined
burst data is sampled a cycle later on the rising edge of S6. Each subsequent pipelined data
burst is single cycle until the last one, which can be held for up to 2 CLKIN cycles after T
A
is asserted. Note that AS and CSx are asserted throughout the burst transfer. This example
shows the timing for external termination, which differs only from the internal termination
example in Figure 18-13 in that the address lines change only at the beginning (assertion of
TS
and TIP) and end (negation of TIP) of the transfer.
Figure 18-12. Line Read Burst (2-1-1-1), External Termination
Figure 18-13 shows timing when internal termination is used.
Table 18-5. Allowable Line Access Patterns
A[3:2] Longword Accesses
00 0–4–8–C
01 4–8–C–0
10 8–C–0–4
11 C–0–4–8
A[31:0], TT[1:0]
R/W
TIP
TS
AS, CSx
D[31:0]
TA
Read
Read
S0 S1 S2 S3 S4 S5 S10S9S8S7S6 S11 S12
Read
Read
CLKIN
BE
/BWEx, OE
TM[2:0], SIZ[1:0]