Datasheet

Chapter 18. Bus Operation 18-15
Data Transfer Operation
Figure 18-17 shows a line burst write with one wait-state insertion.
Figure 18-17. Line Write Burst (3-2-2-2) with One Wait State, Internal Termination
Figure 18-18 shows a burst-inhibited line write. The external device executes a basic write
cycle while determining that a line is being transferred. The external device uses fast
termination to end each subsequent transfer.
Figure 18-18. Line Write Burst-Inhibited, Internal Termination
18.4.7.4 Transfers Using Mixed Port Sizes
Figure 18-19 shows timing for a longword read from an 8-bit port using external
termination. Figure 18-20 shows the same transfer with internal termination. For both,
SIZ[1:0] change only at the start of a new transfer because this burst is implemented as one
A[31:0]
R/W
, TIP
TM[2:0], TT[1:0]
TS
AS, CSx
D[31:0]
T
A
Write
Write
Write
Write
S0 S1 S2 S3 S4 S5 S10S9S8S7S6 S11
WS
WS WS WS
CLKIN
SIZ[1:0]
OE
, BWE
A[31:0]
R/W
, TIP
TT[1:0]
SIZ[1:0]
TS
D[31:0]
T
A
Line
Longword
Basic Fast Fast Fast
A[3:2] = 00 A[3:2] = 01 A[3:2] = 10 A[3:2] = 11
Write Write Write Write
S0 S1 S2 S3 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5
CLKIN
TM[2:0]
AS
, CSx
O
E, BWE