Datasheet

Chapter 18. Bus Operation 18-19
Interrupt Exceptions
• The interrupt request on the interrupt control pins is raised to level 7 and stays there
until an interrupt-acknowledge cycle begins. The level later drops but then returns to
level 7, causing a second transition on the interrupt control lines.
• The interrupt request on the interrupt control pins is raised to level 7 and stays there.
If the level 7 interrupt routine lowers the mask level, a second level 7 interrupt is
recognized without a transition of the interrupt control pins. After the level 7 routine
completes, the MCF5407 compares the mask level to the request level on the IRQ
x
signals. Because the mask level is lower than the requested level, the interrupt mask
is set back to level 7. To ensure it is recognized, the level 7 request on IRQ7
must be
held until the second interrupt-acknowledge bus cycle begins.
18.7.2 Interrupt-Acknowledge Cycle
When the MCF5407 processes an interrupt exception, it performs an interrupt-
acknowledge bus cycle to obtain the vector number that contains the starting location of the
interrupt exception handler. The interrupt-acknowledge bus cycle is a read transfer that
differs from normal read cycles in the following respects:
• TT[1:0] = 0x3 to indicate a CPU space or acknowledge bus cycle.
• TM[2:0] = the level of interrupt being acknowledged.
• A[31:5] = 0x7F_FFFF.
• A[4:2] = the interrupt request level being acknowledged (same as TM[2:0]).
• A[1:0] = 00.
During the interrupt-acknowledge bus cycle (a read cycle), the responding device places the
vector number on D[31:24] and the cycle is terminated normally with T
A. Figure 18-23 is
a flow diagram for an interrupt-acknowledge cycle terminated with T
A.