Datasheet

Chapter 1. Overview 1-1
Chapter 1
Overview
This chapter is an overview of the MCF5407 ColdFire
®
processor. It includes general
descriptions of the modules and features incorporated in the MCF5407, focusing in
particular on new features defined by the Version 4 (V4) programming model, such as the
Harvard memory architecture implementation, new instructions, and new registers.
1.1 Features
The MCF5407 integrated microprocessor combines a V4 ColdFire processor core with the
following components, as shown in Figure 1-1:
• Harvard architecture memory system with 16-Kbyte instruction cache and 8-Kbyte
data cache
• Two, 2-Kbyte on-chip SRAMs
• Integer/fractional multiply-accumulate (MAC) unit
• Divide unit
• System debug interface
• DRAM controller for synchronous and asynchronous DRAM
• Four-channel DMA controller
• Two general-purpose timers
• Two UARTs, one that supports synchronous operations
•I
2
C™ interface
• Parallel I/O interface
• System integration module (SIM)
Designed for embedded control applications, the MCF5407 delivers 233 Dhrystone MIPS
at 162 MHz while minimizing system costs.