Datasheet

Chapter 18. Bus Operation 18-27
General Operation of External Master Transfers
Figure 18-28. Two-Wire Implicit and Explicit Bus Mastership
In Figure 18-28, the external device is master during C1 and C2. It releases bus control in
C3 by asserting BG
to the MCF5407. During C4 and C5, the MCF5407 is implicit master
because no internal access is pending. In C5, an internal bus request becomes pending,
causing the MCF5407 to become explicit bus master in C6 by asserting BD
. In C7, the
external device removes the bus grant to the MCF5407. The MCF5407 does not release the
bus (the MCF5407 continues to assert BD
) until the transfer ends.
NOTE:
The MCF5407 can start a transfer in the clock cycle after BG
is asserted. The external master must not assert BG to the
MCF5407 while driving the bus or the part may be damaged.
Figure 18-29 is a MCF5407 bus arbitration state diagram. States are described in
Table 18-6.
R/W
TIP
TS
AS
D[31:0]
TA
BG
BD
External Master
Explicit
Mastership
Implicit
Mastership
C1 C2 C4 C5 C6 C7C3 C8 C9
MCF5407
CLKIN
A[31:0], TT[1:0]
SIZ[1:0], TM[2:0]