Datasheet

Chapter 18. Bus Operation 18-29
General Operation of External Master Transfers
18.9.2 Multiple External Bus Device Arbitration Protocol
(Three-Wire Mode)
Three-wire mode lets the MCF5407 share the external bus with multiple external devices.
This mode requires an external arbiter to assign priorities to each potential master and to
determine which device accesses the external bus. The arbiter uses the MCF5407 bus
arbitration signals, BR
, BD, and BG, to control use of the external bus by the MCF5407.
The MCF5407 requests the bus from the external bus arbiter by asserting BR
when the core
requests an access. It continues to assert BR
until after the transfer starts. It can negate BR
at any time regardless of the BG status. If the MCF5407 is granted the bus when an internal
bus request is generated, it asserts BD
and the access begins immediately. The MCF5407
always drives BR
and BD, which cannot be directly wire-ORed with other devices.
The external arbiter asserts BG
to grant the bus to MCF5407, which can begin a bus cycle
after the next rising edge of CLKIN. If BG
is negated during a bus cycle, the MCF5407
releases the bus when the cycle completes. To guarantee that the bus is released, BG
must
be negated before the rising edge of the CLKIN in which the last T
A is asserted. Note that
the MCF5407 treats any series of burst or a burst-inhibited transfers as a single bus cycle
and does not release the bus until the last transfer of the series completes.
When the MCF5407 is granted the bus after it asserts BR
, one of two things can occur. If
the MCF5407 has an internal bus request pending, it asserts BD
, indicating explicit bus
mastership, and begins the pending bus cycle by asserting TS
. The MCF5407 continues to
assert BD
until the external bus arbiter negates BG, after which BD is negated at the
completion of the bus cycle. As long as BG
is asserted, BD remains asserted to indicate that
the MCF5407 is bus master, and the MCF5407 continuously drives the address bus,
attributes, and control signals.
If no internal request is pending, the MCF5407 takes implicit bus mastership. It does not
drive the bus and does not assert BD
if the bus has an implicit master. If an internal bus
request is generated, the MCF5407 assumes explicit bus mastership and immediately
begins an access and asserts BD
. Figure 18-30 shows implicit and explicit bus mastership
due to generation of an internal bus request.
1
Both normal terminations and terminations due to bus errors generate an end of cycle. Bus cycles resulting from
a burst-inhibited transfer are considered part of that original transfer.
2
A means asserted.
3
N means negated.
4
EM means external master.