Datasheet

18-34 MCF5407 User’s Manual
Reset Operation
18.10.1 Master Reset
To perform a master reset, an external device asserts RSTI. When power is applied to the
system, external circuitry should assert RSTI
for a minimum of 16 CLKIN cycles after
EVcc and IVcc are within tolerance. Figure 18-33 is a functional timing diagram of the
master reset operation, showing relationships among E/IVcc, RSTI
, mode selects, and bus
signals. CLKIN must be stable by the time E/IVcc reach the minimum operating
specification. See Section 20.1.1, “Supply Voltage Sequencing and Separation Cautions.”
CLKIN should start oscillating as E/IVcc are ramped up to clear out contention internal to
the MCF5407 caused by the random states of internal flip-flops on power up. RSTI
is
internally synchronized for two CLKIN cycles before being used and must meet the
specified setup and hold times in relationship to CLKIN to be recognized.
Figure 18-33. Master Reset Timing
During the master reset period, all signals capable of being three-stated are driven to a
high-impedance; all others are negated. When RSTI
negates, all bus signals remain in a
high-impedance state until the MCF5407 is granted the bus and the core begins the first bus
cycle for reset exception processing. A master reset causes any bus cycle (including DRAM
refresh cycle) to terminate and initializes registers appropriately for a reset exception.
Note that during reset D[7:0] are sampled on the negating edge of RSTI
for initial
MCF5407 configurations listed in Table 18-12.
RSTI
D[7:0]
Bus Signals
BD
BR
RSTO
50K CLKIN cycles
PLL lock time
>16 CLKIN cycles
EVCC, IVCC
CLKIN