Datasheet

19-2 MCF5407 User’s Manual
JTAG Signal Descriptions
that this logic does not affect system or debug operation.
Figure 19-1 is a block diagram of the MCF5407 implementation of the 1149.1 IEEE
standard. The test logic includes several test data registers, an instruction register,
instruction register control decode, and a 16-state dedicated TAP controller.
Figure 19-1. JTAG Test Logic Block Diagram
19.2 JTAG Signal Descriptions
JTAG operation on the MCF5407 is enabled when MTMOD0 is high (logic 1), as described
in Table 19-1. Otherwise, JTAG TAP signals, TCK, TMS, TDI, TDO, and TRST
, are
interpreted as the debug port pins. MTMOD0 should not be changed while RSTI
is
asserted.
Test Data Registers
TDI
TMS
TRST
TDO
V+
V+
V+
Boundary Scan Register
ID Code
Bypass
3-Bit Instruction Register
3-Bit Instruction Decode
M
U
X
TA P
M
U
X
TCK