Datasheet

19-6 MCF5407 User’s Manual
JTAG Register Descriptions
The IEEE Standard 1149.1 requires the EXTEST, SAMPLE/PRELOAD, and BYPASS
instructions. IDCODE, CLAMP, and HIGHZ are optional standard instructions that the
MCF5407 implementation supports and are described in the IEEE Standard 1149.1.
19.4.2 IDCODE Register
The MCF5407 includes an IEEE Standard 1149.1-compliant JTAG identification register,
IDCODE, which is read by the MCF5407 JTAG instruction encoded as octal 1.
Table 19-3 describes IDCODE bit assignments.
CLAMP
(CMP)
Optional 110 Selects the bypass register and asserts functional reset while forcing all output and
bidirectional pins configured as outputs to fixed, preloaded values in the
boundary-scan update registers. Enhances test efficiency by reducing the overall shift
path to one bit (the bypass register) while conducting an EXTEST type of instruction
through the boundary-scan register. CLAMP becomes active on the falling edge of
TCK in the Update-IR state when instruction-shift register data is equivalent to octal 6.
BYPASS
(BYP)
Required 111 Selects the single-bit bypass register, creating a single-bit shift register path from TDI
to the bypass register to TDO. Enhances test efficiency by reducing the overall shift
path when a device other than the MCF5407 is under test on a board design with
multiple chips on the overall 1149.1 defined boundary-scan chain. The bypass register
is implemented in accordance with 1149.1 so the shift register stage is set to logic 0
on the rising edge of TCK following entry into the capture-DR state. Therefore, the first
bit shifted out after selecting the bypass register is always a logic 0 (to differentiate a
part that supports an IDCODE register from a part that supports only the bypass
register).
BYPASS goes active on the falling edge of TCK in the Update-IR state when
instruction shift register data is equivalent to octal 7.
31 30 29 28 2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Version Number
(0000 for initial MCF5407 device)
0100110000000111000000011101
Figure 19-3. IDCODE Register
Table 19-3. IDCODE Bit Assignments
Bits Description
31–28 Version number. Indicates the revision number of the MCF5407
27–22 Design center. Indicates the ColdFire design center
21–12 Device number. Indicates an MCF5407
11–1 Indicates the reduced JEDEC ID for Motorola. Joint Electron Device Engineering Council (JEDEC)
Publication 106-A and Chapter 11 of the IEEE Standard 1149.1 give more information on this field.
0 Identifies this as the JTAG IDCODE register (and not the bypass register) according to the IEEE Standard
1149.1
Table 19-2. JTAG Instructions (Continued)
Instruction Class IR Description