Datasheet

19-10 MCF5407 User’s Manual
Restrictions
19.4.4 JTAG Bypass Register
The IEEE Standard 1149.1-compliant bypass register creates a single-bit shift register path
from TDI to the bypass register to TDO when the BYPASS instruction is selected.
19.5 Restrictions
Test logic design is static, so TCK can be stopped in high or low state with no data loss.
However, system logic uses a different system clock not internally synchronized to TCK.
Operation mixing 1149.1 test logic with system functional logic that uses both clocks must
coordinate and synchronize these clocks externally to the MCF5407.
19.6 Disabling IEEE Standard 1149.1 Operation
There are two ways to use the MCF5407 without IEEE Standard 1149.1 test logic being
active:
101 O.Pin D26 I/O 221 O.Pin A8 I/O
102 I.Pin D26 I/O 222 I.Pin A8 I/O
103 O.Pin D27 I/O 223 O.Pin A7 I/O
104 I.Pin D27 I/O 224 I.Pin A7 I/O
105 O.Pin D28 I/O 225 O.Pin A6 I/O
106 I.Pin D28 I/O 226 I.Pin A6 I/O
107 O.Pin D29 I/O 227 O.Pin A5 I/O
108 I.Pin D29 I/O 228 I.Pin A5 I/O
109 O.Pin D30 I/O 229 O.Pin A4 I/O
110 I.Pin D30 I/O 230 I.Pin A4 I/O
111 O.Pin D31 I/O 231 O.Pin A3 I/O
112 I.Pin D31 I/O 232 I.Pin A3 I/O
113 O.Pin SDA OD 233 O.Pin A2 I/O
114 I.Pin SDA I 234 I.Pin A2 I/O
115 O.Pin SCL OD 235 O.Pin A1 I/O
116 I.Pin SCL I 236 I.Pin A1 I/O
117 O.Pin BE3
O 237 O.Pin A0 I/O
118 O.Pin BE2
O 238 I.Pin A0 I/O
119 O.Pin BE1
O
Table 19-4. Boundary-Scan Bit Definitions
Bit Cell Type Pin Cell Pin Type Bit Cell Type Pin Cell Pin Type