Datasheet

Chapter 19. IEEE 1149.1 Test Access Port (JTAG) 19-11
Obtaining the IEEE Standard 1149.1
• Nonuse of JTAG test logic by either nontermination (disconnection) or intentionally
fixing TAP logic values. The following issues must be addressed if IEEE Standard
1149.1 logic is not to be used when the MCF5407 is assembled onto a board.
— IEEE Standard 1149.1 test logic must remain transparent and benign to the
system logic during functional operation. To ensure that the part enters the
test-logic-reset state requires either connecting TRST
to logic 0 or connecting
TCK to a source that supplies five rising edges and a falling edge after the fifth
rising edge. The recommended solution is to connect TRST
to logic 0.
— TCK has no internal pull-up as is required on TMS, TDI, and TRST
; therefore,
it must be terminated to preclude mid-level input values. Figure 19-4 shows pin
values recommended for disabling JTAG with the MCF5407 in JTAG mode.
Figure 19-4. Disabling JTAG in JTAG Mode
• Disabling JTAG test logic by holding MTMOD0 low during reset (debug mode).
This allows the IEEE Standard 1149.1 test controller to enter test-logic-reset state
when TRST
is internally asserted to the controller. TAP pins function as debug mode
pins. In JTAG mode, inputs TDI/DSI, TMS/BKPT
, and TRST/DSCLK have internal
pull-ups enabled. Figure 19-5 shows pin values recommended for disabling JTAG in
debug mode.
Figure 19-5. Disabling JTAG in Debug Mode
19.7 Obtaining the IEEE Standard 1149.1
The IEEE Standard 1149.1 JTAG specification is a copyrighted document and must be
TDI/DSI
TCK
VDD
TRST
/DSCLK
TMS/BKPT
•
•
•
Note: MTMOD0 high allows JTAG mode.
TDI/DSI
TCK
Debug Interface
TRST/DSCLK
TMS/BKPT
Note: MTMOD0 low prohibits JTAG.