Datasheet

1-4 MCF5407 User’s Manual
MCF5407 Features
1.2 MCF5407 Features
The following list summarizes MCF5407 features:
• ColdFire processor core
— Variable-length RISC, clock-multiplied Version 4 microprocessor core
— Implementation of Revision B of the ColdFire instruction set architecture (ISA),
which leverages the 68K programming model
— Two independent decoupled pipelines: four-stage instruction fetch pipeline (IFP)
and five-stage operand execution pipeline (OEP)
— Ten-instruction FIFO buffer provides decoupling between the pipelines
— Limited superscalar design achieves performance levels close to dual-issue
performance
— Programmable two-level branch acceleration mechanism with an 8-entry branch
cache plus a 128-entry prediction table for increased performance
— 32-bit internal address bus supporting 4 Gbytes of linear address space
— 32-bit data bus
— 16 user-accessible, 32-bit-wide, general-purpose registers
— Supervisor/user modes for system protection
— Vector base register to relocate exception-vector table
— Optimized for high-level language constructs
• Multiply and accumulate unit (MAC)
— High-speed, complex arithmetic processing for DSP applications
— Tightly coupled to the OEP
— Three-stage execute pipeline with one clock issue rate for 16 x 16 operations
— 16 x 16 and 32 x 32 multiplies support, all with 32-bit accumulate
— Signed or unsigned integer support, plus signed fractional operands
• Hardware integer divide unit
— Unsigned and signed integer divide support
— Tightly coupled to the OEP
— 32/16 and 32/32 operation support producing quotient and/or remainder results
• 16-Kbyte instruction cache, 8-Kbyte data cache
— Four-way set-associative organization
— Operates at higher processor core frequency
— Provides pipelined, single-cycle access to critical code and data
— Data cache supports write-through and copyback modes
— Four-entry, 32-bit store buffer to improve performance of operand writes