Datasheet

20-6 MCF5407 User’s Manual
Input/Output AC Timing Specifications
Figure 20-5. PSTCLK Timing
20.3 Input/Output AC Timing Specifications
Table 20-6 lists specifications for parameters shown in Figure 20-6 and Figure 20-7. Note
that inputs IRQ
[7,5,3,1], BKPT, and AS are synchronized internally; that is, the logic level
is validated if the value does not change for two consecutive rising CLKIN edges. Setup
and hold times must be met only if recognition on a particular clock edge is required.
Table 20-7 lists specifications for timings in Figure 20-6, Figure 20-7, and Figure 20-13.
Although output signals that share a specification number have approximately the same
timing, due to loading differences, they do not necessarily change at the same time.
However, they have similar timings; that is, minimum and maximum times are not mixed.
Table 20-6. Input AC Timing Specification
Num Characteristic
54 MHz CLKIN
Units
Min Max
B1
1
1
Inputs: BG, TA, A[23:0], PP[15:0], SIZ[1:0], R/W, TS, EDGESEL, D[31:0],
IRQ
[7,5,3,1], and BKPT
Valid to CLKIN rising (setup) 7.5 — nS
B2
1
CLKIN rising to invalid (hold) 1.0 — nS
B3
2
2
Inputs: AS
Valid to CLKIN rising (setup) 0 — nS
B4
2
CLKIN rising to invalid (hold) 0.5(C1) + 1.3 — nS
B5
3
3
Inputs: D[31:0]
CLKIN to input high impedance — 2 Bus clock
B6 CLKIN to EDGESEL delay 0 5.0 nS
Table 20-7. Output AC Timing Specification
Num Characteristic
54 MHz CLKIN
Units
Min Max
B10
1,2,3
CLKIN rising to valid
— 8
4
nS
— 10
5
nS
B11
3,4,5
CLKIN rising to invalid (hold) 1.0
5
— nS
B12
6,7
CLKIN to high impedance (three-state) — 10 nS
PSTCLK
C6 C6
C5