Datasheet

Chapter 20. Electrical Specifications 20-9
Input/Output AC Timing Specifications
Figure 20-7. SDRAM Read Cycle with EDGESEL Tied to Buffered CLKIN
Figure 20-8 shows an SDRAM write cycle with EDGESEL tied to buffered CLKIN.
A[31:0]
TS
SRAS
SCAS
1
D[31:0]
ACTV NOP PALLNOP
RAS
READ
Row Column
EDGESEL
DRAMW
CAS
B16
B15
B15
B16
B2
B1
B16
B16
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
CLKIN
1
DACR[CASL] = 2
B6
NOP
NOP