Datasheet

20-12 MCF5407 User’s Manual
Input/Output AC Timing Specifications
Figure 20-10. SDRAM Write Cycle with EDGESEL Tied High
Figure 20-11 shows an SDRAM read cycle with EDGESEL tied low.
A[31:0]
TS
SRAS
SCAS
1
D[31:0]
ACTV PALLNOP
RAS
WRITE
Row Column
CLKIN
DRAMW
CAS
B11
B10
B10
B11
B11
B11
0
1 2 3 4 5 6 7 8 9 10 11 12
B10
NOP
1
DACR[CASL] = 2