Datasheet

Chapter 20. Electrical Specifications 20-13
Input/Output AC Timing Specifications
Figure 20-11. SDRAM Read Cycle with EDGESEL Tied Low
Figure 20-12 shows an SDRAM write cycle with EDGESEL tied low.
A[31:0]
TS
SRAS
D[31:0]
ACTV NOP PALLNOP
RAS
READ
Row Column
CLKIN
0
DRAMW
CAS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
B14
B13
B13
B14
B2
B1
B14
B14
SCAS
1
1
DACR[CASL] = 2
NOP