Datasheet

20-18 MCF5407 User’s Manual
I
2
C Input/Output Timing Specifications
20.7 I
2
C Input/Output Timing Specifications
Table 20-11 lists specifications for the I
2
C input timing parameters shown in Figure 20-18.
Table 20-12 lists specifications for the I
2
C output timing parameters shown in
Figure 20-18.
Figure 20-18 shows timing for the values in Table 20-11 and Table 20-12.
Table 20-11. I
2
C Input Timing Specifications between SCL and SDA
Num Characteristic
54 MHz CLKIN
Units
Min Max
I1 Start condition hold time 2 — Bus clocks
I2 Clock low period 8 — Bus clocks
I3 SCL/SDA rise time (V
IL
= 0.5 V to V
IH
= 2.4 V) — 1mS
I4 Data hold time 0 — nS
I5 SCL/SDA fall time (V
IH
= 2.4 V to V
IL
= 0.5 V) — 1mS
I6 Clock high time 4 — Bus clocks
I7 Data setup time 0 — nS
I8 Start condition setup time (for repeated start condition only) 2 — Bus clocks
I9 Stop condition setup time 2 — Bus clocks
Table 20-12. I
2
C Output Timing Specifications between SCL and SDA
Num Characteristic
54 MHz CLKIN
Units
Min Max
I1
1
1
Programming IFDR with the maximum frequency (IFDR = 0x20) results in the minimum output timings listed
here. The I
2
C interface is designed to scale the data transition time, moving it to the middle of the SCL low
period. The actual position is affected by the prescale and division values programmed in IFDR.
Start condition hold time 6 — Bus clocks
I2
1
Clock low period 10 — Bus clocks
I3
2
2
Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the time
SCL or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
SCL/SDA rise time (V
IL
= 0.5 V to V
IH
= 2.4 V) Note 2 Note 2
I4
1
Data hold time 7 — Bus clocks
I5
3
3
Specified at a nominal 50-pF load.
SCL/SDA fall time (V
IH
= 2.4 V to V
IL
= 0.5 V) — 3nS
I6
1
Clock high time 10 — Bus clocks
I7
1
Data setup time 2 — Bus clocks
I8
1
Start condition setup time (for repeated start condition only) 20 — Bus clocks
I9
1
Stop condition setup time 10 — Bus clocks