Datasheet

1-6

MCF5407 User’s Manual

MCF5407 Features

•I

C module

— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and

keypads

— Fully compatible with industry-standard I

C bus

— Master or slave modes support multiple masters

— Automatic interrupt generation with programmable level

• System interface module (SIM)

— Chip selects provide direct interface to 8-, 16-, and 32-bit SRAM, ROM,

FLASH, and memory-mapped I/O devices

— Eight fully programmable chip selects, each with a base address register

— Programmable wait states and port sizes per chip select

— User-programmable processor clock/input clock frequency ratio

— Programmable interrupt controller

— Low interrupt latency

— Four external interrupt request inputs

— Programmable autovector generator

— Software watchdog timer

• 16-bit general-purpose I/O interface

• IEEE 1149.1 test (JTAG) module

• System debug support

— Real-time trace for determining dynamic execution path while in emulator mode

— Background debug mode (BDM) for debug features while halted

— Real-time debug support, including 13 user-visible hardware breakpoint

registers supporting 8 separate breakpoints

— Supports servicing of critical, real-time interrupt requests while the BDM is in

emulator mode

— Supports comprehensive emulator functions through trace and breakpoint logic

• On-chip PLL

— Accepts various clock input (CLKIN) frequencies between 25 and 54 MHz

— Supports core frequencies between 100 and 162 MHz

— Supports low-power mode

• Product offerings

— 233 Dhrystone MIPS at 162 MHz

— Implemented in 0.22 µ, quad-layer-metal process technology with 1.8-V

operation (3.3-V compliant I/O pads)

— 208-pin plastic QFP package

— 0°–70° C operating temperature