Datasheet

A-2 MCF5407 User’s Manual
Instruction Set Additions
A.2 Instruction Set Additions
The MCF5407 implements Revision B (Rev B) of the ColdFire instruction set, which adds
instructions and enhances existing ISA Revision A (Rev A) opcodes to support byte- and
Caches 8-Kbyte unified cache 16-Kbyte instruction cache
8-Kbyte data cache
Section A.3,
“Enhanced
Memories”
Two cache access control
registers (ACR0/ACR1)
ACR0/ACR1 configure data space;
ACR2/ACR3 configure instruction space
4-Kbyte SRAM Two independently configurable 2-Kbyte
SRAMs
No cache locking Ability to lock all or half of the caches to prevent
instructions or data from being cast out. This is
useful for deterministic code.
DMA
modifications
DMA acknowledge assertion
is encoded on TM[2:0].
DACK[1:0] multiplexed on TM[1:0] can be
programmed as separate DMA acknowledge
signals.
DMA TM[2:0] encodings are different from
MCF5307 DMA TM[2:0] encodings.
Section A.4,
“On-Chip DMA
Modifications”
DMA byte count register
(BCR) can be programmed
to be 16 or 24 bits.
BCR is 24 bits only.
UART Both UARTs have identical
functionality. No support for
synchronous mode.
UART0 is identical to the MCF5307 UARTs;
UART1 has been enhanced to provide
synchronous operation and a CODEC interface
for soft modem support.
Section A.5, “UART
Enhancements”
Timing
relationships
All signal timing with respect
to BCLKO; CLKIN rise time =
5 nS.
All signal timings with respect to CLKIN
(BCLKO support provides compatibility with
MCF5307 designs.)
Tighter negative edge bus specifications due to
duty cycle; CLKIN rise time = 2 nS.
Section A.6.1,
“Phase-Locked
Loop (PLL),” and
Section A.6, “Timing
Differences”
Reset
initialization
Need to drive D[7:0]/
AA, PS[1:0],
ADDR_CONFIG,
FREQ[1:0], DIVIDE[1:0]
Need to drive D[7:0]/AA, PS[1:0],
ADDR_CONFIG, BE_CONFIG, DIVIDE[2:0]
Section A.7, “Reset
Initialization
Modifications”
Debug
module
Debug Revision B. Separate
PST[3:0] and DDATA[3:0]
Debug Revision C—Adds breakpoint registers,
normal interrupt request service during debug,
and combines debug signals into
PSTDDATA[7:0]
Section A.8,
“Revision C Debug”
Voltage input
changes
Drives minimum 2.4 V;
accepts 5-V input
Drives minimum 2.4 V; accepts 3.3-V input Section A.9,
“Voltage Input
Changes”
Requires 3.3-V operating
voltage
Requires 1.8-V and 3.3-V operating voltages
Pin
assignment
Standard MCF5307 pinout Compatible with MCF5307 pinout except for
power-pad input assignment
Section A.11,
“Pin-Assignment
Compatibility”
Table A-1. Differences between MCF5307 and MCF5407
Feature MCF5307 MCF5407 Reference