Datasheet

A-4 MCF5407 User’s Manual
On-Chip DMA Modifications
Note that the existing functionality has not changed; new registers and new bits in existing
registers have been added to support the enhanced memories and control for the new branch
cache. One of the two 2-Kbyte SRAMs can be dedicated to support the instruction cache,
and the other can support the data cache. Many designs use one SRAM block as a system
stack and the other to hold important interrupt service routines.
The SRAM can also function as a ROM by programming it as a data block while loading
configuration information to it and then reprogramming it as a read-only instruction block.
The two MCF5407 SRAM blocks can be programmed to provide a contiguous 4-Kbyte
memory map similar to the MCF5307’s single contiguous 4-Kbyte SRAM.
A.4 On-Chip DMA Modifications
The MCF5407 integrates the four-channel DMA used in the MCF5307 with changes to pin
multiplexing, DMA byte transfer count, and the encoding of transfer acknowledgement.
The MCF5307 provides DMA acknowledgement encodings for channels 0 and 1 through
the transfer modifier pins, TM[2:1], which are multiplexed with PP[4:3]. For clarification
on MCF5307 signal multiplexing, see the pinout tables in the mechanical specifications
chapter of the MCF5307 User’s Manual. The MCF5307 also indicates a DMA single
address access through transfer modifier pin TM0, multiplexed with PP2. For more details
see, Chapter 12, “DMA Controller Module”.
When the pin assignment register (PAR) is programmed to enable the TM signals, the
encodings listed in Table A-3 and Table A-4 are driven during transfers by the internal
DMA channels of the MCF5307. The condition TT[1:0] = 01 indicates an access by either
an internal DMA or an external device.
Table A-2. MOVEC CPU Space Register Map
Rc[1:0] Register Definition
0x002 Cache control register (CACR)
0x004 Cache access control register 0 (ACR0; data cache)
0x005 Cache access control register 1 (ACR1; data cache)
0x006 Cache access control register 2 (ACR2; instruction cache)
0x007 Cache access control register 3 (ACR3; instruction cache)
0xC04 RAM base address register 0 (RAMBAR0)
1
1
Either or both of the RAMBAR registers can be configured for instructions or data through
an additional bit, RAMBARn[D/I].
0xC05 RAM base address register 1 (RAMBAR1)
1
Table A-3. TM[2:1] Encoding for MCF5307 Internal DMA as Master (TT = 01)
TM[2:1] Transfer Modifier Encoding
00 DMA acknowledges negated
01 DMA acknowledge, channel 0