Datasheet

Appendix A. Migrating from the ColdFire MCF5307 to the MCF5407 A-7
Timing Differences
Figure A-3. PLL Module
Similar to the MCF5307 functionality, the MCF5407 samples clock ratio encodings on the
lower data bits of the bus at reset to determine the CLKIN-to-PCLK ratio at which the
device runs. These bits are DIVIDE[1:0] on the MCF5307 and are multiplexed with data
bits D[1:0]. Because the MCF5407 offers more divide ratio combinations than the
MCF5307, three input bits, D[2:0]/DIVIDE[2:0], have been provided to offer more
programming options at reset. Also, note that only specific CLKIN ranges are allowed for
each divide ratio on the MCF5407.
Table A-5 shows the new encodings. Note that they differ from the MCF5307 DIVIDE[1:0]
encodings.
A.6.2 Timing Relationships
For both the MCF5307 and MCF5407, the user provides the clock input signal (CLKIN),
which is also used for on-chip peripherals, as shown in Figure A-3. This signal is also the
reference from which other clock frequencies are derived, including the bus clock output
signal (BCLKO), which on the MCF5407 is provided for compatibility with MCF5307
designs. BCLKO is generated by the PLL and MCF5307 designs should use BCLKO as the
bus timing reference for external devices; MCF5407 designs should use CLKIN. On the
MCF5407, the CLKIN frequency can be 1/3, 1/4, 1/5, or 1/6 of the PCLK. Furthermore,
depending on the MCF5307 configuration, the BCLKO-to-PCLK ratio may not be the same
as the CLKIN-to-PCLK ratio. For more details see Section 20.2, “Clock Timing
Specifications”.
On the MCF5407, the user-provided CLKIN should be used as the bus clock for the system.
Table A-5. Divide Ratio Encodings
D[2:0]/DIVIDE[2:0] Multiplier
00x–010 Reserved
011 3
100 4
101 5
110 6
111 Reserved
PLL
CLKIN
RSTI
PSTCLK
Debug Module
DIVIDE[2:0]
RSTO
PCLK (to core)
BCLKO
CLKIN (to on-chip peripherals)
÷2
(= PCLK/2)