Datasheet

A-8 MCF5407 User’s Manual
Reset Initialization Modifications
BCLKO runs at the same frequency as CLKIN and is offered as an optional timing
reference for backwards compatibility for lower-speed MCF5307 designs.
Regardless of the CLKIN frequency driven at power-up, CLKIN and BCLKO have the
same ratio value to PCLK. Although designers can use either BCLKO or CLKIN as a clock
reference, Motorola recommends using CLKIN because it leaves more room to meet bus
specifications than BCLKO, which is generated as a phase-aligned signal to CLKIN. An
MCF5307 user should consider switching to a CLKIN reference clock when upgrading to
the MCF5407 if board frequencies exceed 50 MHz.
Although the CLKIN duty cycle remains the same for the MCF5307 and MCF5407, use
caution when interfacing signals on the falling edge of CLKIN with only a 4-nS window at
high frequencies. Also, note that the MCF5407 input rise time is reduced to 2 nS (5 nS in
the MCF5307). For designers who choose to reference signals from CLKIN only, BCLKO
can be disabled to save power. For details see Section 7.2.3, “Reduced-Power Mode”.
A.7 Reset Initialization Modifi cations
Like the MCF5307, the MCF5407 samples a group of eight input signals, D[7:0], on the
rising edge of CLKIN before the rising edge of RSTI
to determine the reset configuration
of the global chip select, the address bus, and PLL. However, unlike the MCF5307, the
frequency range encodings are not sampled on D[3:2], which are replaced by two other
reset configuration inputs. First, the CLKIN-to-PCLK ratio allows more combinations.
This extra bit is now sampled on D2 so that the clock ratio programming bits encompass
D[2:0]/DIVIDE[2:0].
Second, a new reset configuration bit, BE_CONFIG, is now multiplexed with D3 in the
MCF5407. This bit enables the four byte enables for the global chip select, CS0, for reads
and writes or writes only, depending on the bit value sampled at reset, as shown in
Table A-10.
Table A-6 shows the multiplexing of D[7:0] for the MCF5307 and the MCF5407.
Table A-7 through Table A-10 list the various reset encodings for the configuration signals
Table A-6. D[7:0] Multiplexing
Data Pins MCF5307 MCF5407
D7 AA
D[6:5] PS[1:0]
D4 ADDR_CONFIG
D3 FREQ1 BE_CONFIG, BE[3:0]
D2 FREQ0 DIVIDE2
D1 DIVIDE1
D0 DIVIDE0