Datasheet
Appendix A. Migrating from the ColdFire MCF5307 to the MCF5407 A-9
Reset Initialization Modifications
multiplexed with D[7:3]. See for D[2:0]/DIVIDE[2:0] encodings sampled at reset. Note
that Table A-7 and Table A-8 configure the global, or boot, CS0
that is used to access boot
ROM out of reset. CS0
is the only chip select active out of reset until other chip selects
become valid. Both the wait states and port size of boot memory accessed by boot CS0
are
programmed through these bits.
Table A-8 shows configurations for D[6:5]/PS[1:0].
Table A-9 initializes the pin assignment register of the parallel I/O port to be either parallel
I/O or to be the upper address bus bits along with various attribute and control signals at
reset to give the user the option to access a broader addressing range of memory, if desired.
Table A-10 shows configurations for D3/BE_CONFIG. Because some boot memories
require byte enables to be active only during writes, the functionality of byte enables,
BE[3:0], can be programmed at reset.
D[2:0]/DIVIDE[2:0] configurations are shown in Table A-5.
After RSTI
is negated, 32 bits of CPU configuration information are loaded into data
register D0 and 32 bits of internal memory information are loaded in D1. Because these
registers are completely uninitialized on previous ColdFire devices, this feature allows
users to identify the MCF5407 through software. Values D1 = 0x0630_0530 and D0 =
Table A-7. D7/AA, Automatic Acknowledge of Boot CS0
D7/AA Boot CS0 AA Configuration at Reset
0 Disabled
1 Enabled with 15 wait states
Table A-8. D[6:5]/PS[1:0], Port Size of Boot CS0
D[6:5]/PS[1:0] Boot CS0 Port Size at Reset
00 32-bit port
01 8-bit port
1x 16-bit port
Table A-9. D4/ADDR_CONFIG, Address Pin Assignment
D4/ADDR_CONFIG Configuration Pin Assignment Register at Reset
0 PP[15:0], defaulted to inputs upon reset
1 ADDR[31:24]/TIP/DREQ[1:0]/TM[2:1]
Table A-10. D3/BE_CONFIG, BE[3:0] Boot Configuration
D3/BE_CONFIG Configuration of Byte Enables for Boot CS0
0 BE[3:0] are enabled as byte write enables only
1 BE[3:0] are enabled as byte enables for reads and writes