Datasheet

Appendix B. List of Memory Maps B-3
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]
0x080 Chip-select address register—bank 0 (CSAR0)
[p. 10-6]
Reserved
1
0x084 Chip-select mask register—bank 0 (CSMR0) [p. 10-7]
0x088 Reserved
1
Chip-select control register—bank 0 (CSCR0)
[p. 10-8]
0x08C Chip-select address register—bank 1 (CSAR1)
[p. 10-6]
Reserved
1
0x090 Chip-select mask register—bank 1 (CSMR1) [p. 10-7]
0x094 Reserved
1
Chip-select control register—bank 1 (CSCR1)
[p. 10-8]
0x098 Chip-select address register—bank 2 (CSAR2)
[p. 10-6]
Reserved
1
0x09C Chip-select mask register—bank 2 (CSMR2) [p. 10-7]
0x0A0 Reserved
1
Chip-select control register—bank 2 (CSCR2)
[p. 10-8]
0x0A4 Chip-select address register—bank 3 (CSAR3)
[p. 10-6]
Reserved
1
0x0A8 Chip-select mask register—bank 3 (CSMR3) [p. 10-7]
0x0AC Reserved
1
Chip-select control register—bank 3 (CSCR3)
[p. 10-8]
0x0B0 Chip-select address register—bank 4 (CSAR4)
[p. 10-6]
Reserved
1
0x0B4 Chip-select mask register—bank 4 (CSMR4) [p. 10-7]
0x0B8 Reserved
1
Chip-select control register—bank 4 (CSCR4)
[p. 10-8]
1
Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to
these reserved address spaces and reserved register bits have no effect.
Table B-4. DRAM Controller Registers
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]
0x100 DRAM control register (DCR) [p. 11-3] Reserved
0x104 Reserved
0x108 DRAM address and control register 0 (DACR0) [p. 11-3]
0x10C DRAM mask register block 0 (DMR0) [p. 11-3]
0x110 DRAM address and control register 1 (DACR1) [p. 11-3]
0x114 DRAM mask register block 1 (DMR1) [p. 11-3]
Table B-3. Chip-Select Registers (Continued)
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]