Datasheet

Appendix B. List of Memory Maps B-5
0x1D0 (Read) UART input port
change
registers—(UIPCRn)
[p. 14-17]
—
(Write) UART auxiliary
control
registers
1
—(UACRn)
[p. 14-17]
—
0x1D4 (Read) UART interrupt
status
registers—(UISRn)
[p. 14-18]
—
(Write) UART interrupt
mask
registers—(UIMRn)
[p. 14-18]
—
0x1D8 UART divider upper
registers—(UDUn)
[p. 14-19]
—
0x1DC UART divider lower
registers—(UDLn)
[p. 14-19]
—
0x1E0–
0x1EC
Do not access
2
—
0x1F0 UART interrupt vector
register—(UIVRn)
[p. 14-20]
—
0x1F4 (Read) UART input port
registers—(UIPn)
[p. 14-20]
—
(Write) Do not access
2
—
0x1F8
(Read) Do not access
2
—
(Write) UART output
port bit set command
registers—(UOP1n
3
)
[p. 14-21]
—
0x1FC
(Read) Do not access
2
—
(Write) UART output
port bit reset command
registers—(UOP0n
3
)
[p. 14-21]
—
1
UMR1n, UMR2n, UCSRn, and UACRn[BRG] should be changed only after the receiver/transmitter is issued a
software reset command. That is, if channel operation is not disabled, undesirable results may occur.
2
This address is for factory testing. Reading this location results in undesired effects and possible incorrect
transmission or reception of characters. Register contents may also be changed.
Table B-6. UART0 Control Registers (Continued)
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]