Datasheet

B-6 MCF5407 User’s Manual
3
Address-triggered commands
Table B-7. UART1 Control Registers
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]
UART1 Control Registers
0x200 UART mode
registers
1
—(UMR1n)[p.
14-5], (UMR2n) [p. 14-7
Rx FIFO threshold
register—(RXLVL)
[p. 14-8]
Modem control
register—(MODCTL)
[p. 14-9]
Tx FIFO threshold
register—(TXLVL)
[p. 14-10]
0x204 (Read) UART status
registers—(USRn)
[p. 14-10]
— (Read) Rx samples
available
register—(RSMP)
[p. 14-12]
(Read) Tx space
available
register—(TSPC)
[p. 14-13]
(Write) UART
clock-select
register
1
—(UCSRn)
[p. 14-12]
0x208 (Read) Do not access
2
—
(Write) UART command
registers—(UCRn)
[p. 14-13]
—
0x20C (Read) UART receiver buffers—(URBn) [p. 14-15]
(Write) UART transmitter buffers—(UTBn) [p. 14-16]
0x210 (Read) UART input port
change
registers—(UIPCRn)
[p. 14-17]
—
(Write) UART auxiliary
control
registers
1
—(UACRn)
[p. 14-17]
—
0x214 (Read) UART interrupt
status
registers—(UISRn)
[p. 14-18]
—
(Write) UART interrupt
mask
registers—(UIMRn)
[p. 14-18]
—
0x218 UART divider upper
registers—(UDUn)
[p. 14-19]
—
0x21C UART divider lower
registers—(UDLn)
[p. 14-19]
—
0x220–
0x22C
Do not access
2
—