Datasheet

Appendix B. List of Memory Maps B-7
0x230 UART interrupt vector
register—(UIVRn)
[p. 14-20]
—
0x234 (Read) UART input port
registers—(UIPn)
[p. 14-20]
—
(Write) Do not access
2
—
0x238 (Read) Do not access
2
—
(Write) UART output
port bit set command
registers—(UOP1n
3
)
[p. 14-21]
—
0x23C
(Read) Do not access
2
—
(Write) UART output
port bit reset command
registers—(UOP0n
3
)
[p. 14-21]
—
0x200 UART mode
registers
4
—(UMR1n)
[p. 14-5], (UMR2n)
[p. 14-7]
Rx FIFO threshold
register—(RXLVL)
[p. 14-10] (UART1 only)
Modem control
register—(MODCTL)
[p. 14-9] (UART1 only)
Tx FIFO threshold
register—(TXLVL)
[p. 14-10] (UART1 only)
0x204 (Read) UART status
registers—(USRn)
[p. 14-10]
— (Read) Rx samples
available
register—(RSMP)
[p. 14-12] (UART1 only)
(Read) Tx space
available
register—(TSPC)
[p. 14-13] (UART1 only)
(Write) UART
clock-select
register
1
—(UCSRn)
[p. 14-12]
1
UMR1n, UMR2n, UCSRn, and UACRn[BRG] should be changed only after the receiver/transmitter is issued a
software reset command. That is, if channel operation is not disabled, undesirable results may occur.
2
This address is for factory testing. Reading this location results in undesired effects and possible incorrect
transmission or reception of characters. Register contents may also be changed.
3
Address-triggered commands
4
UMR1n, UMR2n, UCSRn, and UACRn[BRG] should be changed only after the receiver/transmitter is issued a
software reset command. That is, if channel operation is not disabled, undesirable results may occur.
Table B-8. Parallel Port Memory Map
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]
0x244 Parallel port data direction register (PADDR)
[p. 15-2]
Reserved
0x248 Parallel port data register (PADAT) [p. 15-2] Reserved
Table B-7. UART1 Control Registers (Continued)
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]