Datasheet

B-8 MCF5407 User’s Manual
Table B-9. I
2
C Interface Memory Map
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]
0x280 I
2
C address register
(IADR) [p. 8-6]
Reserved
0x284 I
2
C frequency divider
register (IFDR) [p. 8-6]
Reserved
0x288 I
2
C control register
(I2CR) [p. 8-7]
Reserved
0x28C I
2
C status register
(I2SR) [p. 8-8]
Reserved
0x290 I
2
C data I/O register
(I2DR) [p. 8-9]
Reserved
Table B-10. DMA Controller Registers
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]
0x300 Source address register 0 (SAR0) [p. 12-7]
0x304 Destination address register 0 (DAR0) [p. 12-7]
0x308 DMA control register 0 (DCR0) [p. 12-8]
0x30C Reserved Byte count register 0 (BCR0) [p. 12-7]
0x310 DMA status register 0
(DSR0) [p. 12-10]
Reserved
0x314 DMA interrupt vector
register 0 (DIVR0)
[p. 12-11]
Reserved
0x340 Source address register 1 (SAR1) [p. 12-7]
0x344 Destination address register 1 (DAR1) [p. 12-7]
0x348 DMA control register 1 (DCR1) [p. 12-8]
0x34C Reserved Byte count register 1 (BCR1) [p. 12-7]
0x350 DMA status register 1
(DSR1) [p. 12-10]
Reserved
0x354 DMA interrupt vector
register 1 (DIVR1)
[p. 12-11]
Reserved
0x380 Source address register 2 (SAR2) [p. 12-7]
0x384 Destination address register 2 (DAR2) [p. 12-7]
0x388 DMA control register 2 (DCR2) [p. 12-8]
0x38C Reserved Byte count register 2 (BCR2) [p. 12-7]
0x390 DMA status register 2
(DSR2) [p. 12-10]
Reserved