Datasheet

Appendix B. List of Memory Maps B-9
0x394 DMA interrupt vector
register 2 (DIVR2)
[p. 12-11]
Reserved
0x3C0 Source address register 3 (SAR3) [p. 12-7]
0x3C4 Destination address register 3 (DAR3) [p. 12-7]
0x3C8 DMA control register 3 (DCR3) [p. 12-8]
0x3CC Reserved Byte count register 3 (BCR3) [p. 12-7]
0x3D0 DMA status register 3
(DSR3) [p. 12-10]
Reserved
0x3D4 DMA interrupt vector
register 3 (DIVR3)
[p. 12-11]
Reserved
Table B-10. DMA Controller Registers (Continued)
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]