Datasheet

Glossary-2 MCF5407 User’s Manual
system. Caches are coherent if a processor performing a read from
its cache is supplied with data corresponding to the most recent value
written to memory or to another processor’s cache.
Cache flush. An operation that removes from a cache any data from a
specified address range. This operation ensures that any modified
data within the specified address range is written back to main
memory.
Cache line. The smallest unit of consecutive data or instructions that is stored
in a cache. For ColdFire processors a line consists of 16 bytes.
Caching-inhibited. A memory update policy in which the cache is bypassed
and the load or store is performed to or from main memory.
Cast outs. Cache lines that must be written to memory when a cache miss
causes a cache line to be replaced.
Clear. To cause a bit or bit field to register a value of zero. See also Set.
Copyback. A cache memory update policy in which processor write cycles
are directly written only to the cache. External memory is updated
only indirectly, for example, when a modified cache line is cast out
to make room for newer data.
Effective address (EA). The 32-bit address specified for an instruction.
Exception. A condition encountered by the processor that requires special,
supervisor-level processing.
Exception handler. A software routine that executes when an exception is
taken. Normally, the exception handler corrects the condition that
caused the exception, or performs some other meaningful task (that
may include aborting the program that caused the exception). The
address for each exception handler is identified by an exception
vector defined by the ColdFire architecture.
Fetch. The act of retrieving instructions from either the cache or main
memory and making them available to the instruction unit.
Flush. An operation that causes a modified cache line to be invalidated and
the data to be written to memory.
Harvard architecture. An architectural model featuring separate caches for
instruction and data.
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