Datasheet

Glossary of Terms and Abbreviations Glossary-3
Illegal instructions. A class of instructions that are not implemented for a
particular processor. These include instructions not defined by the
ColdFire architecture.
Implementation. A particular processor that conforms to the ColdFire
architecture, but may differ from other architecture-compliant
implementations for example in design, feature set, and
implementation of optional features. The ColdFire architecture has
many different implementations.
Imprecise mode. A memory access mode that allows write accesses to a
specified memory region to occur out of order.
Instruction queue. A holding place for instructions fetched from the current
instruction stream.
Instruction latency. The total number of clock cycles necessary to execute
an instruction and make the results of that instruction available.
Interrupt. An asynchronous exception. On ColdFire processors, interrupts
are a special case of exceptions. See also asynchronous exception.
Invalid state. State of a cache entry that does not currently contain a valid
copy of a cache line from memory.
Least-significant bit (lsb). The bit of least value in an address, register, data
element, or instruction encoding.
Least-significant byte (LSB). The byte of least value in an address, register,
data element, or instruction encoding.
Longword. A 32-bit data element
Master. A device able to initiate data transfers on a bus. Bus mastering refers
to a feature supported by some bus architectures that allow a
controller connected to the bus to communicate directly with other
devices on the bus without going through the CPU.
Memory coherency. An aspect of caching in which it is ensured that an
accurate view of memory is provided to all devices that share system
memory.
Modified state. Cache state in which only one caching device has the valid
data for that address.
H
I
L
L
M