Datasheet

INDEX
Index Index-1
A
Addressing mode summary, 2-15
Arbitration
between masters, 6-14
bus control, 6-11
for internal transfers, 6-12
Architecture
Harvard memory, 2-6
instruction set
additions, 2-18
enhancements, 2-36
B
Branch acceleration, 2-4
Branch instruction execution
timing, 2-30
Bus arbitration control, 6-11
Bus master park register, 6-11
Bus operation
bus errors, 18-17
characteristics, 18-2
control signals, 18-1
data transfer
back-to-back cycles, 18-10
burst cycles
line read bus, 18-12
line transfers, 18-12
line write bus, 18-14
mixed port sizes, 18-15
overview, 18-11
cycle execution, 18-4
cycle states, 18-5
fast-termination cycles, 18-9
operation, 18-2
read cycle, 18-7
write cycle, 18-8
external master transfers
general, 18-21
two-device arbitration protocol, 18-25
two-wire mode, 18-25
features, 18-1
interrupt exceptions, 18-17
misaligned operands, 18-16
reset operation
master, 18-34
overview, 18-33
software watchdog, 18-35
C
Cache
configuration register, 2-12
registers, access control, 2-12
Chip-select module
8-, 16-, and 32-bit port sizing, 10-4
enable signals, 17-15
operation, 10-2
general, 10-3
global, 10-4
overview, 10-1
registers, 10-5, 10-6, B-2
code example, 10-9
control, 10-8
mask, 10-7
signals, 10-1
Clock
PLL control, 6-10
ColdFire core
exception stack frame definition, A-11
features and enhancements, 2-1
Condition code register, 2-9
CPU STOP instruction, 6-10
D
Data registers, A-13
Debug
module enhancements, 2-6
system interface, 1-12
DMA controller module
byte count registers, 12-7
programming model, 12-5
signal description, 12-2
source address registers, 12-7
transfer overview, 12-4
DRAM controller
asynchronous mode signals, 11-4
asynchronous operation
burst page mode, 11-12
continuous page mode, 11-13
extended data out, 11-15
general, 11-4
register set, 11-4
general guidelines, 11-8
non-page mode, 11-11
refresh operation, 11-16
registers, 11-3