Datasheet

INDEX
Index Index-3
signal descriptions, 19-2
TAP controller, 19-3
test logic disabling, 19-10
M
MAC
data representation, 3-4
hardware support, 2-5
instruction execution timings, 3-5
instruction set summary, 3-4
operation, 3-3
programming model, 2-10, 3-2
Mask registers
DRAM, 11-7, 11-22
MBAR, 6-4
Mechanical data, 16-1
case drawing, 16-9
diagram, 16-8
pinout, 16-1
Memory
integer data formats, 2-14
SIM register, 6-3
Modules, 1-7
base address register, 2-12
core description, 1-7
debug, 2-6
DMA controller, 1-9
DRAM controller, 1-9
I
2
C, 1-11
PLL, 1-13
system interface, 1-11
16-bit parallel port, 1-12
chip selects, 1-11
debug, 1-12
external bus, 1-11
interrupt controller, 1-12
JTAG, 1-12
Timer, 1-11
UARTs, 1-10
MOVE instructions timing, 2-25
O
Opcodes
illegal handling, 2-5
P
Parallel port
code example, 15-4
data direction register, 15-2
data register, 15-2
operation, 15-1
Pin assignment register, 6-10, 15-1
Pipelines, 2-2
instruction fetch, 2-4
operand execution, 2-4
PLL, 7-2
clock control for STOP, 6-10
clock frequency relationships, 7-4
clock-multiplied, 2-2
control register, 7-3
modes
normal, 7-2
reduced power, 7-3
operation, 7-2
overview, 7-1
port list, 7-4
power supply filter circuit, 7-6
reset/initialization, 7-2
timing relationships, 7-4
Power supply
filter circuit, 7-6
Program counter, 2-9
Programming models
MAC, 2-10
overview, 2-7
registers, 1-15
SIM, 6-3
summary, B-1
supervisor, 2-10
user, 2-8
R
RAM base address registers, 2-12
Registers
A0–A6, 2-9
A7, 2-9
AATR, 5-10
access control, 2-12
address, 2-9
AVR, 9-5
BAAR, 5-12
bus master park, 6-11
cache configuration, 2-12
CACR, 2-12
CCR, 2-9
chip-select
control, 10-8
mask, 10-7
module, 10-5
condition code, 2-9
CSR, 5-13
D0–D7, 2-8
data, 2-8, A-13
DMA byte count, 12-7
DMA source address, 12-7
DRAM