Datasheet

Chapter 1. Overview 1-13
Programming Model, Addressing Modes, and Instruction Set
To support program trace, the Version 4 debug module has combined the processor status
and debug data outputs into a single 8-bit bus (PSTDDATA[7:0]). This bus and the
PSTCLK output provide execution status, captured operand data, and branch target
addresses defining processor activity at one-half the CPU’s clock rate.
1.3.10 PLL Module
The MCF5407 PLL module is shown in Figure 1-3.
Figure 1-3. PLL Module
The PLL module’s three modes of operation are described as follows.
• Reset mode—When RSTI
is asserted, the PLL enters reset mode. At reset, the PLL
asserts RST
O from the MCF5407. The core:bus frequency ratio and other MCF5407
configuration information are sampled during reset.
• Normal mode—In normal mode, the input frequency programmed at reset is
clock-multiplied to provide the processor clock (PCLK).
• Reduced-power mode—In reduced-power mode, the PCLK is disabled by executing
a sequence that includes programming a control bit in the system configuration
register (SCR) and then executing the STOP instruction. Register contents are
retained in reduced-power mode, so the system can be reenabled quickly when an
unmasked interrupt or reset is detected.
1.4 Programming Model, Addressing Modes, and
Instruction Set
The ColdFire programming model has two privilege levels—supervisor and user. The S bit
in the status register (SR) indicates the privilege level. The processor identifies a logical
address that differentiates between supervisor and user modes by accessing either the
supervisor or user address space.
PLL
CLKIN
RSTI
Debug Module
DIVIDE[2:0]
RSTO
PCLK (to core)
BCLKO
CLKIN (to on-chip peripherals)
÷2
PSTCLK (= PCLK/2)