Datasheet

vi MCF5407 User’s Manual
CONTENTS
Paragraph
Number
Title
Page
Number
1.4.3 Supervisor Registers ..................................................................................... 1-16
1.4.4 Instruction Set ............................................................................................... 1-16
Part I
MCF5407 Processor Core
Chapter 2
ColdFire Core
2.1 Features and Enhancements................................................................................ 2-1
2.1.1 Clock-Multiplied Microprocessor Core.......................................................... 2-2
2.1.2 Enhanced Pipelines ......................................................................................... 2-2
2.1.2.1 Instruction Fetch Pipeline (IFP).................................................................. 2-4
2.1.2.1.1 Branch Acceleration ............................................................................... 2-4
2.1.2.2 Operand Execution Pipeline (OEP) ............................................................ 2-4
2.1.2.2.1 Illegal Opcode Handling......................................................................... 2-5
2.1.2.2.2 Hardware Multiply/Accumulate (MAC) Unit ........................................ 2-5
2.1.2.2.3 Hardware Divide Unit............................................................................. 2-6
2.1.2.3 Harvard Memory Architecture ................................................................... 2-6
2.1.3 Debug Module Enhancements ........................................................................ 2-6
2.2 Programming Model ........................................................................................... 2-7
2.2.1 User Programming Model .............................................................................. 2-8
2.2.1.1 Data Registers (D0–D7) ............................................................................. 2-8
2.2.1.2 Address Registers (A0–A6)........................................................................ 2-9
2.2.1.3 Stack Pointer (A7, SP)................................................................................ 2-9
2.2.1.4 Program Counter (PC) ................................................................................ 2-9
2.2.1.5 Condition Code Register (CCR)................................................................. 2-9
2.2.1.6 MAC Programming Model....................................................................... 2-10
2.2.2 Supervisor Programming Model................................................................... 2-10
2.2.2.1 Status Register (SR).................................................................................. 2-11
2.2.2.2 Vector Base Register (VBR) .................................................................... 2-12
2.2.2.3 Cache Control Register (CACR) .............................................................. 2-12
2.2.2.4 Access Control Registers (ACR0–ACR3)................................................ 2-12
2.2.2.5 RAM Base Address Registers (RAMBAR0 and RAMBAR1) ................ 2-12
2.2.2.6 Module Base Address Register (MBAR) ................................................. 2-12
2.3 Integer Data Formats......................................................................................... 2-13
2.4 Organization of Data in Registers..................................................................... 2-13
2.4.1 Organization of Integer Data Formats in Registers ...................................... 2-13
2.4.2 Organization of Integer Data Formats in Memory ....................................... 2-14
2.5 Addressing Mode Summary ............................................................................. 2-15
2.6 Instruction Set Summary................................................................................... 2-15
2.6.1 Additions to the Instruction Set Architecture ............................................... 2-18