Datasheet

Chapter 2. ColdFire Core 2-1
Chapter 2
ColdFire Core
This chapter provides an overview of the microprocessor core of the MCF5407. The
chapter begins with a description of enhancements from the Version 3 (V3) ColdFire core,
and then fully describes the V4 programming model as it is implemented on the MCF5407.
It also includes a full description of exception handling, data formats, an instruction set
summary, and a table of instruction timings.
2.1 Features and Enhancements
The MCF5407 is the first standard product to contain a Version 4 ColdFire microprocessor
core. To create this next-generation, high-performance core, many advanced
microarchitectural techniques were implemented. Most notable are a Harvard memory
architecture, branch cache acceleration logic, and limited superscalar dual-instruction issue
capabilities, which together provide 233 (Dhrystone 2.1) MIPS performance at 162 MHz.
The MCF5407 core design emphasizes performance and backward compatibility, and
represents the next step on the ColdFire performance roadmap.
The following list summarizes MCF5407 features:
• Variable-length RISC, clock-multiplied Version 4 microprocessor core
• Revision B of the ColdFire instruction set architecture provides new instructions to
improve performance and code density
• Two independent, decoupled pipelines—four-stage instruction fetch pipeline (IFP)
and five-stage operand execution pipeline (OEP) for increased performance of
conditional branch instructions
• Ten-instruction FIFO buffer provides decoupling between the pipelines
• Limited superscalar design approaches dual-issue performance
• Sophisticated two-level branch acceleration mechanism with a branch cache plus a
prediction table for increased performance of conditional Bcc instructions
• 32-bit internal address bus supporting 4 Gbytes of linear address space
• 32-bit data bus
• 16 user-accessible, 32-bit-wide, general-purpose registers
• Supervisor/user modes for system protection