Datasheet

2-2 MCF5407 User’s Manual

Features and Enhancements

• Vector base register to relocate exception-vector table

• Optimized for high-level language constructs

2.1.1 Clock-Multiplied Microprocessor Core

The MCF5407 incorporates a clock-multiplying phase-locked loop (PLL). Increasing the

internal speed of the core also allows higher performance while providing the system

designer with an easy-to-use lower speed system interface.

The frequency of the processor complex is an integer multiple of the external bus speed.

Chapter 20, “Electrical Speciﬁcations,” lists the supported clock ratios.

The processor, instruction and data caches, integrated SRAMs, and misalignment module

operate at the higher speed clock (PCLK); other system integrated modules operate at the

speed of the input clock (CLKIN). When combined with the enhanced pipeline structure of

the Version 4 ColdFire core, the processor and its local memories provide a high level of

performance for today’s demanding embedded applications.

PCLK can be disabled to minimize dissipation when a low-power mode is entered. This is

described in Section 7.2.3, “Reduced-Power Mode.”

2.1.2 Enhanced Pipelines

The IFP prefetches instructions. The OEP decodes instructions, fetches required operands,

then executes the speciﬁed function. The two independent, decoupled pipeline structures

maximize performance while minimizing core size. Pipeline stages are shown in Figure 2-1

and are summarized as follows:

• Four-stage IFP (plus optional instruction buffer stage)

— Instruction address generation (IAG) calculates the next prefetch address.

— Instruction fetch cycle 1 (IC1) initiates prefetch on the processor’s local

instruction bus.

— Instruction fetch cycle 2 (IC2) completes prefetch on the processor’s instruction

local bus.

— Instruction early decode (IED) generates time-critical decode signals needed for

the OEP.

— Instruction buffer (IB) optional stage uses FIFO queue to minimize effects of

fetch latency.

• Five-stage OEP with two optional processor bus write cycles.

— Decode stage (DS/secDS) decodes and selects for two sequential instructions.

— Operand address generation (OAG) generates the address for the data operand.

— Operand fetch cycle 1 and 2 (OC1 and OC2) fetch data operands.

— Execute (EX) performs prescribed operations on previously fetched data

operands.